1. Field of the Invention
This invention relates generally to the packaging of electronic components. More particularly, it relates to a high density circuit package for bonding integrated circuit die pads to associated contact pins. Still more particularly, the invention relates a high density planar array of connector tabs allowing reliable interconnection to associated die tabs.
2. Background of the Invention
The advent of development of integrated circuity has given rise to the need for integrated circuit packages that will both house and protect the integrated circuit die, and will provide a mechanism of making electrical interconnection between the circuits on the integrated circuit die and the contact pins that are utilized to make electrical interconnections to circuits, power, and ground external to the integrated circuit die. In the early stages of development of integrated circuits there were relatively few connections between the integrated circuit die and the external circuitry. For those early types of integrated circuits, the interconnection to the integrated circuit package was relatively straight forward and generally involved an array of connector tabs arranged around a die cavity and adapted to be electrically connected to associated die pads.
In the early integrated circuit development there were relatively few circuit on each integrated circuit die, and the circuit operational rates were by modern day standards relatively slow. Accordingly, the spacing and configuration of the connector tabs with respect to the die pads was relatively less important in the consideration of the length of interconnection conductors and the degree of difficulty of reliable assembly. The number of connector tabs to be located around the die cavity characteristically numbered in the range of twenty to fifty.
As the integrated circuit technology advanced, more circuit cells were able to be fabricated in a similar die area so that substantially increased functionality could be accomplished on a given integrated circuit die. The added functionality and increase in the number of circuits involved generally required a larger number of pins out to the associated external circuitry. As physical sizes decreased and the number of required die pads increased, it was necessary in the prior art to develop integrated circuit packages that would accommodate connections to a larger number of connector tabs. Both integrated circuit users and integrated package manufacturers worked to develop die interconnect systems that would accommodate the higher die pad densities. One approach in the prior art to handling increased densities was to develop a multilayer package that would array groups of connector tabs on separate layers resulting in essentially a step configuration around the die cavity. This necessitated registration of the layers during manufacturing such that the pitch of the connector tabs on the various layers were maintained and that the relationship between layers was maintained so that the connecting wires would remain properly aligned and not result in unwanted short circuits in manufacturing. So long as the pitch of the die pads remained greater than the ability to hold tolerances during manufacture of the integrated circuit package, this approach to providing step connector tabs was workable.
In the first phases of step connector tab development, packages were developed that had connector tabs arrayed on two layers of the integrated circuit connector. Then as the number die pads increased, it was found to be advantageous to deploy the connector tabs on three layers of the integrated circuit connector.
The increase in the amount of circuity incorporated on each die and the increase in the circuit switching rate has resulted in the relatively short interconnection lead through the connector to ground, power and other signal interconnections to be treated as transmission line designs. The step approach to providing die pad to connector tab connection became relatively more difficult to handle, both from the standpoint of fabrication and from the standpoint of differences in conductor lengths affected the circuit operation. Further, the increased number of interconnection conductors and the reduced sizes of the die pads and the connector tabs rendered automated assembly more difficult due to the alignment tolerances between layers of the integrated circuit package.
Integrated circuit packages utilizing the stepped array of connector tabs have been found to be effective up to approximately 400 interconnections of die pads to connector tabs and at the circuit operational rates for die having those numbers of die pads. Beyond these levels manufacturing tolerances cannot be reliably held.
At the present time the state of integrated circuitry has advanced such that more than 500 die pads are arrayed on the integrated circuit die and must be connected to the associated connector tabs. For the physical size of modern day die, the spacing of die pads can be less than 4 mils. Since the registration of multilayers in the integrated circuit die package has a tolerance approaching plus or minus 4 mils, it can be seen that a simple tolerance build up between layers can result in misalignment of connector tabs with respect to the layers that is approximately equal to the spacing of the die pads. This concern makes it relatively impossible to provide an automated bonding process for interconnecting the die pads to their associated connector tabs. Additionally, circuit rates are such that it is essential that the circuit paths to ground and voltage and signal pins be minimized to accommodate circuit operational requirements. It has been determined that the stepped array of connector tabs is not workable for these of levels of circuit operation and die pad densities.